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data sheet no. pd60269 typical connection product summary v offset 200 v max. i o +/- 130 ma/270 ma v out 10 v - 20 v t on/off (typ.) 680 ns/150 ns deadtime (typ.) 520 ns half-bridge driver features ? floating channel designed for bootstrap operation ? fully operational to +200 v ? tolerant to negative transient voltage, dv/dt immune ? gate drive supply range from 10 v to 20 v ? undervoltage lockout ? 3.3 v, 5 v, and 15 v logic compatible ? cross-conduction prevention logic ? matched propagation delay for both channels ? internal set deadtime ? high- side output in phase with hin input ? low- side output out of phase with input description the irs2003 is a high voltage, high speed power mosfe t and igbt drivers wi th dependent high - and low-side referenced output channels. proprietary hvic and latch immune cmos technologies enable rugge- dized monolithic construction. the logic input is compatible with standard cmos or lsttl output, down to 3.3 v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross- conduction. the floating channel can be used to drive an n-channel power mosfet or igbt in the high- side configuration which operates up to 200 v. www.irf.com 1 irs2003(s)pbf (refer to lead assignments for correct configuration). this diagram shows electrical connections only. please refer to our application notes and designtips for proper circuit board layout. packages 8-lead pdip irs2003 8-lead soic irs2003s ? rohs compliant
irs2003(s)pbf www.irf.com 2 symbol definition min. max. units v b high- side floating absolute voltage-0.3225 v s high- side floating supply offset voltagev b - 25v b + 0.3 v ho high- side floating output voltagev s - 0.3v b + 0.3 v cc low- side and logic fixed supply voltage-0.325 v lo low- side output voltage-0.3v cc + 0.3 v in logic input voltage (hin & )-0.3v cc + 0.3 dv s /dt allowable offset supply voltage transient ? 50 v/ns p d package power dissipation @ t a +25 c (8 lead pdip) ? 1.0 (8 lead soic) ? 0.625 rth ja thermal resistance, junction to ambient (8 lead pdip) ? 125 (8 lead soic) ? 200 t j junction temperature ? 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) ? 300 recommended operating conditions the input/output logic timing diagram is shown in fig. 1. for proper operation the device should be used within the recommended conditions. the v s offset rating is tested with all supplies biased at a 15 v differential. symbol definition min. max. units v b high- side floating supply absolute voltagev s + 10v s + 20 v s high- side floating supply offset voltagenote 1200 v ho high- side floating output voltagev s v b v cc low- side and logic fixed supply voltage1020 v lo low- side output voltage0v cc v in logic input voltage (hin & )0v cc t a ambient temperature -40 125 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. note 1: logic operational for v s of -5 v to +2 00 v. logic state held for v s of -5 v to -v bs . (please refer to the design tip dt97-3 for more details). c v v w c/w c
irs2003(s)pbf www.irf.com 3 symbol definition min. typ. max. units t est conditions v ih logic ?1? (hin) & logic ?0? ( ) input voltage 2.5 ? ? v il logic ?0? (hin) & logic ?1? ( ) input voltage ? ? 0.8 v oh high level output voltage, v bias - v o ? 0.05 0.2 v ol low level output voltage, v o ?0.020.1 i lk offset supply leakage current ? ? 50 v b = v s = 200 v i qbs quiescent v bs supply current ? 30 55 i qcc quiescent v cc supply current ? 150 270 i in+ logic ?1? input bias current ? 3 10 hin = 5 v, = 0 v i in- logic ?0? input bias current??5h in = 0 v, = 5 v v ccuv+ v cc supply undervoltage positive going 8 8.9 9.8 threshold v ccuv- v cc supply undervoltage negative going 7.4 8.2 9 threshold i o+ output high short circuit pulsed current 130 290 ? v o = 0 v, v in = v ih pw 10 s i o- output low short circuit pulsed current 270 600 ? v o = 15 v, v in = v il pw 10 s symbol definition min. typ. m ax. units t est conditions t on turn-on propagation delay ? 680 820 v s = 0 v t off turn-off propagation delay ? 150 220 v s = 200 v t r turn-on rise time ? 70 170 t f turn-off fall time ? 35 90 dt deadtime, ls turn-off to hs turn-on & 400 520 650 hs turn-on to ls turn-off mt delay matching, hs & ls turn-on/off ? ? 60 static electrical characteristics v bias (v cc , v bs ) = 15 v and t a = 25 c unless otherwise specified. the v in , v th, and i in parameters are referenced to com. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, c l = 1000 pf and t a = 25 c unless otherwise specified. v ns v ma a v cc = 10 v to 20 v i o = 2 ma v in = 0 v or 5 v
irs2003(s)pbf www.irf.com 4 functional block diagram lead definitions symbol description hinlogic input for high- side gate driver output (ho), in phase logic input for low- side gate driver output (lo), out of phase v b high- side floating supply hohigh- side gate drive output v s high- side floating supply return v cc low- side and logic fixed supply lolow- side gate drive output comlow- side return lead assignments 8 lead pdip 8 lead soic irs2003pbf IRS2003SPBF 1 2 3 4 8 7 6 5 v cc hin lin com v b ho v s lo 1 2 3 4 8 7 6 5 v cc hin lin com v b ho v s lo vb ho vs vcc ihn lin dead time & shoot-through prevention pulse gen pulse filter hv level shift r s q vcc lo com uv detect
irs2003(s)pbf www.irf.com 5 figure 1. input/output timing diagram figure 3. deadtime waveform definitions figure 2. switching time waveform definitions
irs2003(s)pbf www.irf.com 6 turn-on delay time (ns) figure 4a. turn-on time vs. temperature v bias supply voltage (v) figure 4b. turn-on time vs. supply voltage turn-off delay time (ns) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max . typ. turn-off delay time (ns) temperature ( o c) figure 5a. turn-off time vs. temperature v bias supply voltage (v) figure 5b. turn-off time vs. supply voltage 0 200 400 600 800 1000 1200 1400 10 12 14 16 18 20 max. ty p. 0 100 200 300 400 500 10 12 14 16 18 20 max . typ . 0 200 400 600 800 1000 0 2 4 6 8 101214161820 turn-on delay time (ns ) input voltage (v) max . typ . 0 200 400 600 800 1000 1200 1400 -50 -25 0 25 50 75 100 125 max . typ . temperature ( o c) turn-on delay time (ns) figure 4c. turn-on time vs. input voltage 0 200 400 600 800 1000 0 2 4 6 8 1012141618 turn-off delay time (ns ) input voltage (v) max . typ . figure 5c. turn-off time vs. input voltage turn-off delay time (ns)
irs2003(s)pbf www.irf.com 7 figure 7a. turn-off fall time vs. temperature turn-off fall time (ns) turn-off fall time (ns) figure 7b. turn-off fall time vs. voltage temperature ( o c) v bias supply voltage (v) deadtime (ns) figure 8b. deadtime vs. voltage deadtime (ns) figure 8a. deadtime vs. temperature 0 200 400 600 800 1000 1200 1400 10 12 14 16 18 20 max . typ . min . 0 200 400 600 800 1000 1200 1400 -50 - 25 0 25 50 75 100 125 max . ty mi n. p . turn-on rise time (ns) figure 6a. turn-on rise time vs. temperature turn-on rise time (ns) figure 6b. turn-on rise time vs. voltage 0 100 200 300 400 500 10 12 14 16 18 20 m ax. typ. v bias supply voltage (v) 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) max. typ. 0 100 200 300 400 500 10 12 14 16 18 20 0 50 100 150 200 -50 -25 0 25 50 75 100 125 temperature ( o c) 0 50 100 150 200 10 12 14 16 18 20 input voltage (v) max. typ. max. typ. max. typ.
www.irf.com 8 i n p u t v o l t a g e ( v ) figure 10b. logic "0"(hin) & logic "1" ( ) input voltage vs. voltage figure 11a. high level output voltage vs. temperature figure 11b. high level output voltage vs. supply voltage h i g h l e v e l o u t p u t v o l t a g e ( v ) v bias supply voltage (v) i n p u t v o l t a g e ( v ) 0 0.8 1.6 2.4 3.2 4 10 12 14 16 18 20 max. v cc supply voltage (v) 0 0.8 1.6 2.4 3.2 4 -50 -25 0 25 50 75 100 125 max. temperature ( o c) figure 10a. logic "0"(hin) & logic "1" ( ) input voltage vs. temperature temperature ( o c) i n p u t v o l t a g e ( v ) i n p u t v o l t a g e ( v ) figure 9a. logic "1" input voltage vs. temperature figure 9b. logic "1" input voltage vs. supply voltage 1 2 3 4 5 -50 -25 0 25 50 75 100 125 1 2 3 4 5 10 12 14 16 18 20 v bias supply voltage (v) i n p u t v o l t a g e ( v ) 0.0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 min. min. typ. max. typ. max. h i g h l e v e l o u t p u t v o l t a g e ( v ) 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) lin lin pdf created with pdffactory trial version www.pdffactory.com irs2003(s)pbf
irs2003(s)pbf www.irf.com 9 offset supply leakge current ( a) 0 100 200 300 400 500 0 200 400 600 800 ma x . figure 13a. offset supply current vs. temperature figure 13b. offset supply current vs. voltage figure 14a. v bs supply current vs. temperature figure 14b. v bs supply current vs. voltage temperature ( o c) temperature ( o c) v bs supply current ( a) offset supply leakge current ( a) v b boost voltage (v) v bs supply current ( a) v bs floating supply voltage (v) 0 30 60 90 120 150 10 12 14 16 18 20 max . ty p. 0 30 60 90 120 150 - 50-25 0 25 50 75100125 max. typ. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 max . figure 12a. low level output voltage vs. temperature figure 12b. low level output voltage vs. supply voltage low level output voltage (v) low level output voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) 0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v bias supply v oltage (v ) typ. max. typ. max.
irs2003(s)pbf www.irf.com 10 vcc supply voltage (v) figure 16a. logic "1" input current vs. temperature figure 16b. logic "1" input current vs. voltage figure 17a. logic "0" input bias current vs. temperature figure 17b. logic "0" input bias current vs. voltage l o g i c ? 1 ? i n p u t c u r r e n t ( m a ) temperature ( o c) l o g i c ? 0 ? i n p u t b i a s c u r r e n t ( m a ) l o g i c ? 1 ? i n p u t c u r r e n t ( m a ) 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 max. typ. max 0 5 10 15 20 25 30 10 12 14 16 18 20 max. typ. figure 15a. vcc supply current vs. temperature figure 15b. vcc supply current vs. voltage v cc supply current (ma) v cc supply current (ma) 0 100 200 300 400 500 600 700 -50 -25 0 25 50 75 100 125 max. typ. temperature ( o c) 0 100 200 300 400 500 600 700 10 12 14 16 18 20 max. typ. vcc supply voltage (v) max 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature (c) figure 17a. logic "0" input bias current max 0 1 2 3 4 5 6 10 12 14 16 18 20 supply voltage (v) logic "0" input bias current ( m a)
irs2003(s)pbf www.irf.com 11 output source current ( m a) figure 19a. output source current vs. temperature figure 19b. output source current vs. supply voltage figure 20a. output sink current vs. temperature figure 20b. output sink current vs. supply voltage temperature ( o c) v bias supply voltage (v) output sink current ( m a) output source current ( m a) output sink current ( m a) figure 18a. v cc undervoltage threshold(+) vs. temperature figure 18b. v cc undervoltagethreshold (-) vs. temperature temperature ( o c) temperature ( o c) v cc uvlo threshold +(v) 6 7 8 9 10 11 -50 - 25 0 25 50 75 100 125 min. max. typ . typ. v cc uvlo threshold -(v) 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 max . ty p. min. typ. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 0 200 400 600 800 1000 10 12 14 16 18 20 s() typ. min. typ. min. typ. min. typ. min.
irs2003(s)pbf www.irf.com 12 01-6014 01-3003 01 (ms-001ab) 8-lead pdip 01-6027 01-0021 11 (ms-012aa) 8-lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & toleranc ing per asme y14.5m-1994. 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions no t to exc eed 0.25 [.010]. 7 dimension is the length of lead for soldering to a substrate. mold protrusions no t to exc eed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters in c h e s min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic case outlines
irs2003(s)pbf www.irf.com 13 carrier tape dimension for 8soicn code min max min max a 7 .9 0 8.1 0 0. 31 1 0 .3 18 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5 .4 5 5.5 5 0. 21 4 0 .2 18 e 6 .3 0 6.5 0 0. 24 8 0 .2 55 f 5 .1 0 5.3 0 0. 20 0 0 .2 08 g 1 .5 0 n/a 0.059 n/a h 1 .5 0 1.6 0 0. 05 9 0 .0 62 m etr ic im p erial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1 .9 5 2.4 5 0. 76 7 0 .0 96 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 m etr ic im p erial e f a c d g a b h n ot e : co ntrolling d imension in mm loaded tape feed direction a h f e g d b c tape & reel 8-lead soic
irs2003(s)pbf www.irf.com 14 order information 8-lead pdip irs2003pbf 8-lead soic IRS2003SPBF 8-lead soic tape & reel irs2003strpbf ir world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 leadfree part marking information pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code the soic- 8 is msl 2 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at www.irf.com data and specifications subject to change without notice. 11/27/2006 lead free released non-lead free released part number date code irsxxxxx yww? ?xxxx

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